1. Field of the Invention
Generally, the present disclosure relates to integrated circuits including sophisticated transistor elements that comprise advanced gate structures including a metal-containing electrode and a high-k gate dielectric of increased permittivity.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, MOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a material for a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region that is accomplished by decreasing the thickness of the silicon dioxide layer.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered. Possible alternative dielectrics include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
When advancing to sophisticated gate architectures based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance, even at a less critical thickness, compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, a metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Therefore, the threshold voltage of the transistors is significantly affected by the work function of the gate material that is in contact with the gate dielectric material, and an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may require an additional band gap offset for the P-channel transistor. For this reason, it has been proposed to appropriately adjust the threshold voltage of transistor devices by providing a specifically designed semiconductor material at the interface between the gate dielectric material and the channel region of the transistor device, in order to appropriately select the band gap of the specifically designed semiconductor material to the work function of the metal-containing gate electrode material, thereby obtaining the desired threshold voltage of the transistor under consideration. Typically, a corresponding specifically designed semiconductor material, such as silicon/germanium and the like, may be provided by an epitaxial growth technique at an early manufacturing stage, which may also represent an additional complex process step, which, however, may avoid complex processes in an advanced stage for adjusting the work function and thus the threshold voltages in a very advanced process stage.
It turns out, however, that the manufacturing sequence of forming the threshold adjusting semiconductor alloy may have a significant influence on transistor characteristics, as will be described in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 above which is formed a silicon-based semiconductor material 102 having an appropriate thickness for forming therein and thereabove transistor elements. Furthermore, an isolation structure 102C is formed in the semiconductor layer 102, thereby laterally delineating and thus defining active regions 102A, 102B. In this context, an active region is to be understood as a semiconductor material in which an appropriate dopant profile is formed or is to be created in order to form PN junctions for one or more transistor elements. In the example shown in FIG. 1a, the active region 102A corresponds to a P-channel transistor while the active region 102B represents an N-channel transistor. That is, the active regions 102A, 102B comprise an appropriate basic dopant concentration in order to determine the conductivity of a P-channel transistor and an N-channel transistor, respectively. It should be appreciated that the active regions 102A, 102B may comprise or may receive other components, such as germanium, carbon and the like, in order to appropriately adjust the overall electronic characteristics. Similarly, in the active region 102A, an appropriate valence band offset is to be adjusted with respect to a sophisticated gate electrode structure still to be formed by forming an appropriate semiconductor alloy, as will be described later on.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following conventional process strategies. The isolation structure 102C is formed by well-established lithography, etch, deposition, planarization and anneal techniques, in which appropriate hard mask layers, such as a pad oxide and a silicon nitride material, are formed on the semiconductor layer 102, followed by the patterning of a trench in the semiconductor layer 102. Thereafter, the trench is filled with an appropriate insulating material, such as silicon dioxide and the like. It should be appreciated that the process sequence for forming the isolation structure 102C may result in a more or less pronounced stress level in the active regions 102A, 102B. After the removal of any excess material and planarizing the surface topography, the further processing is typically continued by performing a plurality of implantation processes using an appropriate masking regime in order to introduce the required dopant species for generating the basic dopant concentration in the active regions 102A, 102B, as required in view of the transistors to be formed therein and thereabove. After activating the dopant species and re-crystallizing implantation-induced damage, the further processing is continued by removing any material residues, such as oxide materials, and exposing the device 100 to an oxidizing ambient 110, which is typically established on the basis of elevated temperatures, for instance in the range of 700-1200° C. Consequently, during the dry oxidation process 110, a mask layer 104 is formed in a well-controllable manner during the process 110. For example, a maximal thickness of the mask layer 104 is adjusted to 10 nm or less.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, in which an etch mask 105 in the form of a resist material is formed above the semiconductor device 100 such that the active region 102B and a part of the isolation structure 102C, i.e., the mask material 104, are covered by the mask 105, while the active region 102A, i.e., the mask material 104 formed thereon, and the remaining part of the isolation structure 102C, are exposed to a wet chemical etch ambient 111 in order to selectively remove the mask material 104 from the active region 102A. During the etch process 111, which is typically performed on the basis of diluted hydrofluoric acid (HF), the resist material 105 has to withstand the etch attack, wherein, in particular, the edge 105E of the mask 105 positioned above the isolation structure 102C may be increasingly eroded during the etch process 111. For example, an etch time of several minutes may be required in order to reliably remove the mask material 104 from the active region 102A. Due to the increasing erosion of the edge region 105E, the boundary between the mask area and the non-mask area in the isolation region 102C may not be well defined and may thus result in a certain degree of “roughness” due to the varying degree of material erosion, which may affect the further processing of the device 100, in particular when the active regions 102A, 102B represent closely-spaced active regions, which are thus laterally delineated by the isolation region 102C including the eroded surface area.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, i.e., after the selective removal of the mask material 104 from above the active region 102A and after the removal of the etch mask 105 (FIG. 1b). As discussed above, due to the preceding etch sequence based on hydrofluoric acid, a certain material loss may occur in the isolation structure 102C, wherein the increasing mask erosion during the etch process may result in a non-well-defined transition area in the isolation region 102C.
FIG. 1d schematically illustrates the semiconductor device 100 when exposed to a further reactive process ambient 106, which may include a cleaning process and the like in order to prepare the device 100 for the subsequent deposition of a silicon/germanium alloy selectively on the first active region 102A. The process 106 may be established on the basis of any appropriate chemistry in order to remove contaminants and the like which may have been produced during the previous removal of the etch mask and the like. Typically, the cleaning process 106 may cause a certain degree of material erosion of the mask 104, thereby reducing its thickness, as indicated by 104R, however, without exposing the surface portions of the second active region 102B.
FIG. 1e schematically illustrates the semiconductor device 100 during a selective epitaxial growth process 107, in which process parameters, such as temperature, pressure, flow rates of precursor gases and the like, are appropriately selected such that a material deposition is substantially restricted to exposed silicon surface areas, while the silicon dioxide-based surface areas substantially prevent a deposition of material. That is, the deposition process 107 may be adjusted such that a certain degree of deposition selectivity is obtained with respect to silicon material in the active region 102A and any oxide surface areas, such as the deposition mask 104 and the isolation region 102C. As previously explained, the finally-obtained threshold voltage of a transistor to be formed in and above the active region 102A strongly depends on the characteristics of the silicon/germanium material 108, such as the germanium concentration thereof and the thickness, such that precisely determined process conditions have to be established during the process 107. After the deposition of silicon/germanium alloy 108, which is now a part of the active region 102A having the appropriate band gap for forming thereon sophisticated gate electrode structures, the deposition mask 104 is removed, for instance by using hydrofluoric acid, which in turn may also result in a certain material removal in the isolation region 102C, thereby contributing to a further pronounced surface topography between the active regions 102A, 102B and the isolation region 102C, which may additionally have a pronounced surface topography due to the previously-performed etch process 111 as described with reference to FIG. 1b. 
FIG. 1f schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, in which a transistor 150A is formed in and above the active region 102A, which now includes at least a portion of the silicon/germanium alloy 108. Similarly, a transistor 150B is formed in and above the active region 102B. Moreover, the transistors 150A, 150B, for instance representing a P-channel transistor and an N-channel transistor, respectively, comprise gate electrode structures 160A, 160B, respectively. As shown, the gate electrode structure 160A is formed on the threshold adjusting silicon/germanium alloy 108 and comprises a gate dielectric material 161, which includes a high-k dielectric material, wherein the gate dielectric material 161 is covered by a metal-containing electrode material 162. Moreover, a conventional electrode material 163, such as amorphous silicon, polycrystalline silicon and the like, is typically formed above the electrode material 162. Moreover, the sensitive materials 161 and 162 are laterally confined by an appropriate spacer or liner material 165, for instance, provided in the form of a silicon nitride material and the like. Furthermore, a sidewall spacer structure 164, which may comprise one or more spacer elements, possibly in combination with any etch stop liners, is provided according to the process and device requirements. The gate electrode structure 160B has a similar configuration, wherein, however, the gate dielectric material 161 is directly formed on the active region 102B. It should be appreciated that the gate electrode structures 160A, 160B may further differ from each other with respect to the resulting work function of the material layers 162. That is, the transistor 150A may require a different work function so as to obtain, in combination with the silicon/germanium material 108, the desired threshold voltage for a P-channel transistor. To this end, any appropriate work function metal species, such as aluminum, may be incorporated into the layer 162 and/or the gate dielectric layer 161. Similarly, an appropriate work function metal species, such as lanthanum and the like, may be incorporated into the layer 162 and/or the layer 161 of the transistor 150B in order to obtain the desired threshold voltage.
The semiconductor device 100 as shown in FIG. 1f may be formed on the basis of any well-established process techniques, which include the deposition of the materials 161, 162 and 163, possibly in combination with other materials, such as dielectric cap layers, anti-reflective coating (ARC) materials and the like. As discussed above, appropriate patterning regimes and materials may be used for the layers 161 and 162 so as to obtain a desired high capacitive coupling in combination with a superior conductivity, while also a desired work function and thus threshold voltage for the transistors 150A, 150B, wherein the silicon/germanium alloy 108 provides the desired end gap offset. After the patterning of the sophisticated layer stack, at least the sensitive materials 161 and 162 have to be reliably confined in order to not unduly expose these materials to any reactive process atmospheres, which may otherwise result in significant modifications of these materials, which in turn may lead to a significant drift of the resulting threshold voltage. To this end, sophisticated deposition techniques may be applied in order to form the liner 165, followed by appropriate deposition and etch processes for forming a part of the sidewall spacer structure 164, which may then be used to introduce dopant species for forming drain and source regions 153 in the active regions 102A, 102B, respectively. To this end, well-established implantation strategies and masking regimes may be applied. Thereafter, an anneal process may be applied, thereby adjusting the final lateral and vertical profile of the drain and source regions 153, thereby also adjusting the final length of a channel region 152 positioned below the respective gate electrode structures 160A, 160B.
It should be appreciated that, although the above-described process strategy may enable forming sophisticated gate electrode structures and thus transistors, a significant variability of the transistor characteristics therein may, however, be observed. For example, the characteristics of the silicon/germanium alloy 108 may vary in a length direction, i.e., in FIG. 1f the horizontal direction, which may, however, not negatively affect the resulting transistor characteristics. On the other hand, a significant variation of the material characteristics is observed in the transistor width direction, i.e., in a direction perpendicular to the drawing plane of FIG. 1f, wherein basically the same edge effects may be observed, which may, for instance, be caused by a pronounced surface topography between the isolation region 102C and the active region 102A, while other negative influences may be caused by the previously-used deposition mask 104 (FIGS. 1a and 1b) since the formation thereof and the selective removal may result in different conditions in the center of the active region 102A compared to the edge thereof. Furthermore, the irregular surface topography of the isolation region 102C, in particular between closely-spaced transistor devices, may also affect the process of forming the protective liner or spacer 165, which in turn may result in a deterioration of the sensitive materials 161 and 162 in one or both of the transistors 150A, 150B, which, thus, may also contribute to significant yield losses.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.